View LTC1409_1482517.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 LTC1409 12-bit, 800ksps sampling a/d converter with shutdown s f ea t u re d u escriptio the ltc ? 1409 is a 1 m s, 800ksps, sampling 12-bit a/d converter that draws only 80mw from 5v supplies. this easy-to-use device includes a high dynamic range sample- and-hold and a precision reference. two digitally selectable power shutdown modes provide flexibility for low power systems. the LTC1409 full-scale input range is 2.5v. maximum dc specs include 1lsb inl and 1lsb dnl over tem- perature. outstanding ac performance includes 72.5db s/(n + d) at the nyquist input frequency of 400khz. the unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 20mhz bandwidth. the 60db common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. the adc has a m p compatible, 12-bit parallel output port. there is no pipeline delay in the conversion results. a separate convert start input and a data ready signal (busy) ease connections to fifos, dsps and micropro- cessors. a digital output driver power supply pin allows direct connection to 3v logic. n sample rate: 800ksps n power dissipation: 80mw n 72.5db s/(n + d) and 86db thd at nyquist n no pipeline delay n nap (4mw) and sleep (10 m w) shutdown modes n operates with internal 15ppm/ c reference or external reference n true differential inputs reject common mode noise n 20mhz full power bandwidth sampling n 2.5v bipolar input range n 28-pin so wide and ssop package u s a o pp l ic at i n telecommunications n digital signal processing n multiplexed data acquisition systems n high speed data acquisition n spectrum analysis n imaging systems , ltc and lt are registered trademarks of linear technology corporation. u a o pp l ic at i ty p i ca l 800khz, 12-bit sampling a/d converter effective bits and signal-to-(noise + distortion) vs input frequency 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +a in ? in v ref refcomp agnd d11(msb) d10 d9 d8 d7 d6 d5 d4 dgnd av dd ov dd v ss busy cs convst rd shdn nap/slp ognd d0 d1 d2 d3 LTC1409 10 m f differential analog input (?.5v to 2.5v) 2.50v v ref output 10 m f 10 m f ?v 5v 12-bit parallel bus m p control lines LTC1409 ?ta01 input frequency (hz) 2 effective bits s/(n + d) (db) 4 6 8 10 10k 100k 1m 10m LTC1409 ?ta02 0 1k 12 74 68 62 56 50 nyquist frequency f sample = 800ksps
2 LTC1409 av dd = ov dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................ 6v negative supply voltage (v ss )................................ C 6v total supply voltage (v dd to v ss ) .......................... 12v analog input voltage (note 3) .................................. v ss C 0.3v to v dd + 0.3v digital input voltage (note 4) ............ v ss C 0.3v to 10v digital output voltage ............. v ss C 0.3v to v dd + 0.3v power dissipation ............................................. 500mw operating temperature range LTC1409c............................................... 0 c to 70 c LTC1409i ........................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c a u g w a w u w a r b s o lu t exi t i s wu u package / o rder i for atio consult factory for military grade parts. order part number LTC1409cg LTC1409csw LTC1409ig LTC1409isw parameter conditions min typ max units resolution (no missing codes) l 12 bits integral linearity error (note 7) l 0.3 1 lsb differential linearity error l 0.3 1 lsb offset error (note 8) 2 6 lsb l 8 lsb full-scale error 15 lsb full-scale tempco i out(ref) = 0 l 15 ppm/ c cc hara terist ics co u verter with internal reference (notes 5, 6) symbol parameter conditions min typ max units v in analog input range (note 9) 4.75v v dd 5.25v, C 5.25v v ss C 4.75v l 2.5 v i in analog input leakage current cs = high l 1 m a c in analog input capacitance between conversions 17 pf during conversions 5 pf t acq sample-and-hold acquisition time l 50 150 ns t ap sample-and-hold aperture delay time C1.5 ns t jitter sample-and-hold aperture delay time jitter 5 ps rms cmrr analog input common mode rejection ratio C 2.5v < (Ca in = +a in ) < 2.5v 60 db (note 5) put u i a a u log 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +a in ? in v ref refcomp agnd d11(msb) d10 d9 d8 d7 d6 d5 d4 dgnd av dd ov dd v ss busy cs convst rd shdn nap/slp ognd d0 d1 d2 d3 sw package 28-lead plastic so wide g package 28-lead plastic so top view t jmax = 110 c, q ja = 95 c/w (g) t jmax = 110 c, q ja = 130 c/w (sw)
3 LTC1409 symbol parameter conditions min typ max units s/(n + d) signal-to-noise plus distortion ratio 100khz input signal (note 12) l 70 73.0 db 400khz input signal (note 12) l 68 72.5 db thd total harmonic distortion 100khz input signal, first five harmonics C 90 db 400khz input signal, first five harmonics l C 86 C 74 db peak harmonic or spurious noise 400khz input signal l C 90 C 74 db imd intermodulation distortion f in1 = 29.37khz, f in2 = 32.446khz C 84 db full power bandwidth 15 mhz full linear bandwidth s/(n + d) 3 68db 1.6 mhz (note 5) accuracy ic dy u w a parameter conditions min typ max units v ref output voltage i out = 0 2.480 2.500 2.520 v v ref output tempco i out = 0 15 ppm/ c v ref line regulation 4.75v v dd 5.25v 0.01 lsb/v C 5.25v v ss C 4.75v 0.01 lsb/v v ref output resistance C 0.1ma | i out | 0.1ma 4 k w refcomp output voltage i out = 0 4.06 v (note 5) i ter al refere ce characteristics u uu (note 5) symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 5pf v oh high level output voltage v dd = 4.75v i o = C 10 m a 4.5 v i o = C 200 m a l 4.0 v v ol low level output voltage v dd = 4.75v i o = 160 m a 0.05 v i o = 1.6ma l 0.10 0.4 v i oz high-z output leakage d11 to d0 v out = 0v to v dd , cs high l 10 m a c oz high-z output capacitance d11 to d0 cs high (note 9 ) l 15 pf i source output source current v out = 0v C 10 ma i sink output sink current v out = v dd 10 ma (note 5) digital i puts a d digital outputs u u power require e ts w u symbol parameter conditions min typ max units v dd positive supply voltage (notes 10, 11) 4.75 5.25 v v ss negative supply voltage (note 10) C 4.75 C 5.25 v i dd positive supply current cs high l 6.0 9.0 ma nap mode convst = cs = rd = shdn = 0v, nap/slp = 5v 0.8 1.2 ma sleep mode convst = cs = rd = shdn = 0v, nap/slp = 0v 1.0 m a
4 LTC1409 power require e ts w u (note 5) ti i g characteristics w u symbol parameter conditions min typ max units f sample(max) maximum sampling frequency l 800 khz t conv conversion time l 900 1250 ns t acq acquisition time l 150 ns t 1 cs to rd setup time (notes 9, 10) l 0ns t 2 cs to convst setup time (notes 9, 10) l 10 ns t 3 nap/slp to shdn setup time (notes 9, 10) l 10 ns t 4 shdn - to convst wake-up time (note 10) 200 ns t 5 convst low time (notes 10, 11) l 50 ns t 6 convst to busy delay c l = 25pf 10 ns l 60 ns t 7 data ready before busy - 20 35 ns l 15 ns t 8 delay between conversions (note 10) l 40 ns t 9 wait time rd after busy - l C5 ns t 10 data access time after rd c l = 25pf 15 35 ns l 45 ns c l = 100pf 20 45 ns l 60 ns t 11 bus relinquish time 830 ns 0 c t a 70 c l 35 ns C40 c t a 85 c l 40 ns t 12 rd low time l t 10 ns t 13 convst high time l 50 ns t 14 aperture delay of sample-and-hold C 1.5 ns note 5: v dd = 5v, f sample = 800khz, t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for a single- ended +a in input with Ca in grounded. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111. note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. the l indicates specifications which apply over the full operating temperature range; all other limits and typicals t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd and agnd wired together (unless otherwise noted). note 3: when these pin voltages are taken below v ss or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss or above v dd without latch-up. note 4: when these pin voltages are taken below v ss they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss without latchup. these pins are not clamped to v dd . (note 5) symbol parameter conditions min typ max units i ss negative supply current cs high l 10 15 ma nap mode convst = cs = rd = shdn = 0v, nap/slp = 5v 10 m a sleep mode convst = cs = rd = shdn = 0v, nap/slp = 0v 1 m a p diss power dissipation l 80 120 mw nap mode convst = cs = rd = shdn = 0v, nap/slp = 5v 3.8 6 mw sleep mode convst = cs = rd = shdn = 0v, nap/slp = 0v 0.01 mw
5 LTC1409 note 11: the falling convst edge starts a conversion. if convst returns high at a critical point during the conversion it can create small errors. for best results ensure that convst returns high either within 650ns after conversion start or after busy rises. ti i g characteristics w u note 12: signal-to-noise ratio (snr) is measured at 100khz and distortion is measured at 400khz. these results are used to calculate signal-to-noise plus distortion (sinad). typical perfor m a n ce characteristics u w s/(n + d) vs input frequency and amplitude input frequency (hz) 1k signal/(noise + distortion) (db) 80 70 60 50 40 30 20 10 0 10k 100k LTC1409 ?tpc01 1m 10m v in = 0db v in = 20db v in = 60db input frequency (hz) 1k signal/(noise + distortion) (db) 80 70 60 50 40 30 20 10 0 10k 100k LTC1409 ?tpc02 1m 10m signal-to-noise ratio vs input frequency spurious-free dynamic range vs input frequency input frequency (hz) 10k spurious-free dynamic range (db) 0 10 20 30 40 50 60 70 80 90 100 100k 1m 10m LTC1409 ?tpc04 distortion vs input frequency input frequency (hz) amplitude (db below the fundamental) 0 10 20 30 40 50 60 70 80 90 100 1k 100k 1m 10m LTC1409 ?tpc03 10k thd 3rd 2nd intermodulation distortion plot frequency (hz) 0 amplitude (db) 0 20 40 60 80 100 120 100k 200k 300k 400k LTC1409 ?tpc05 50k 150k 250k 350k fb ?fa 2fb ?fa 2fa ?fb 2fa 2fb 3fb fa + 2fb 3fa 2fa + fb f sample = 800khz f in1 = 88.19580078khz f in2 = 111.9995117khz fa + fb
6 LTC1409 typical perfor m a n ce characteristics u w input common mode rejection vs input frequency power supply feedthrough vs ripple frequency ripple frequency (hz) amplitude of power supply feedthrough (db) 0 10 20 30 40 50 60 70 80 90 100 1k 100k 1m 10m LTC1409 ?tpc08 10k v ss v dd dgnd input frequency (hz) 1k common mode rejection (db) 80 70 60 50 40 30 20 10 0 10k 100k lt1409 ?tpc09 1m 10m d3 to d0 (pins 15 to 18): three-state data outputs. ognd (pin 19): digital ground for output drivers. tie to agnd. nap/slp (pin 20): power shutdown mode. selects the mode invoked by the shdn pin. low selects sleep mode and high selects quick wake-up nap mode. shdn (pin 21): power shutdown input. a low logic level will invoke the shutdown mode selected by the nap/slp pin. rd (pin 22): read input. this enables the output drivers when cs is low. pi fu ctio s uu u +a in (pin 1): positive analog input, 2.5v. Ca in (pin 2): negative analog input, 2.5v. v ref (pin 3): 2.50v reference output. refcomp (pin 4): 4.06v reference output. bypass to agnd using 10 m f tantalum in parallel with 0.1 m f or 10 m f ceramic. agnd (pin 5): analog ground. d11 to d4 (pins 6 to 13): three-state data outputs. dgnd (pin 14): digital ground for internal logic. tie to agnd. integral nonlinearity vs output code output code 0 inl error (lsb) 1.00 0.50 0 0.50 1.00 512 1024 1536 2048 lt1409 ?tpc07 2560 3072 3584 4096 differential nonlinearity vs output code output code 0 dnl error (lsb) 1.00 0.50 0 0.50 1.00 512 1024 1536 2048 lt1409 ?tpc06 2560 3072 3584 4096
7 LTC1409 pi fu ctio s uu u convst (pin 23): conversion start signal. this active low signal starts a conversion on its falling edge. cs (pin 24): chip select. the input must be low for the adc to recognize convst and rd inputs. busy (pin 25): the busy output shows the converter status. it is low when a conversion is in progress. data valid on the rising edge of busy. v ss (pin 26): C 5v negative supply. bypass to agnd using 10 m f tantalum in parallel 0.1 m f or 10 m f ceramic. ov dd (pin 27): positive supply for output drivers. for 5v logic, short to pin 28. for 3v logic, short to supply of the logic being driven. av dd (pin 28): 5v positive supply. bypass to agnd 10 m f tantalum in parallel with 0.1 m f or 10 m f ceramic. load circuits for bus relinquish time load circuits for access timing 1k 100pf 100pf dbn dbn 1k 5v LTC1409 ?tc02 1k c l c l dbn dbn 1k 5v LTC1409 ?tc01 (a) hi-z to v oh and v ol to v oh (b) hi-z to v ol and v oh to v ol (a) v oh to hi-z (b) v ol to hi-z fu ctio al block diagra uu w 12-bit capacitive dac comp ref amp 2.5v ref 4k refcomp (4.06v) c sample c sample ? ? d11 d0 busy control logic cs convst rd shdn internal clock nap/slp zeroing switches ov dd ognd av dd +a in ? in v ref agnd dgnd 12 LTC1409 ?bd + successive approximation register output latches test circuits
8 LTC1409 applicatio n s i n for m atio n wu u u conversion details the LTC1409 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. the adc is complete with a precision reference and an internal clock. the control logic provides easy interface to microproces- sors and dsps. (please refer to the digital interface section for the data format.) conversion start is controlled by the cs and convst inputs. at the start of the conversion the successive approximation register (sar) is reset. once a conversion cycle has begun it cannot be restarted. during the conversion, the internal differential 12-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the +a in and Ca in inputs are connected to the sample-and-hold capacitors (c sample ) during the acquire phase and the comparator offset is nulled by the zeroing switches. in this acquire phase, a minimum delay of 150ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. during the convert phase the comparator zeroing switches open, putting the comparator into compare mode. the input switches connect the c sample capacitors to ground, transferring the differential analog input charge onto the summing junction. this input charge is successively com- pared with the binary-weighted charges supplied by the differential capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the differential dacs output balances the +a in and Ca in input charges. the sar contents (a 12-bit data word) which represents the difference of +a in and Ca in are loaded into the 12-bit output latches. dynamic performance the LTC1409 has excellent high speed sampling capabil- ity. fft (fast four transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using fft algorithm, the adcs spectral content can be examined for frequen- cies outside the fundamental. figure 2 shows typical LTC1409 plots. figure 1. simplified block diagram comp +c sample ? dac ? ? d11 d0 zeroing switches hold hold +a in ? in +c dac ? sample 12 LTC1409 ?f01 + sar output latches +v dac ? dac hold hold figure 2b. LTC1409 nonaveraged, 4096 point fft, input frequency = 375khz frequency (khz) 0 amplitude (db) 100 200 300 400 lt1409 ?f02b 0 20 40 60 80 100 120 50 150 250 350 f sample = 800khz f in = 375khz sfdr = 89db sinad = 72.5db figure 2a. LTC1409 nonaveraged, 4096 point fft, input frequency = 100khz frequency (khz) 0 amplitude (db) 100 200 300 400 lt1409 ?f02a 0 20 40 60 80 100 120 50 150 250 350 f sample = 800khz f in = 97.45khz sfdr = 89.1db sinad = 73.1db
9 LTC1409 applicatio n s i n for m atio n wu u u signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 2 shows a typical spectral content with an 800khz sampling rate and a 100khz input. the dynamic performance is excellent for input frequencies up to and beyond the nyquist limit of 400khz. effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: n = [s/(n + d) C 1.76]/6.02 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 800khz the LTC1409 maintains near ideal enobs up to the nyquist input frequency of 400khz. refer to figure 3. thd vvv vn v = +++? 20 log 234 1 222 2 where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. thd vs input frequency is shown in figure 4. the LTC1409 has good distortion performance up to the nyquist frequency and beyond. input frequency (hz) effective bits 12 11 10 9 8 7 6 5 4 3 2 1 0 1k 100k 1m 10m LTC1409 ?f03 10k f sample = 800khz figure 3. effective bits and signal/(noise + distortion) vs input frequency total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: figure 4. distortion vs input frequency intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the dc transfer function can create distortion products at the sum and difference frequencies of mfa + Cnfb, where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (fa + fb). if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula: imd fa fb + () = 20 log amplitude at (fa + fb) amplitude at fa peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this input frequency (hz) amplitude (db below the fundamental) 0 10 20 30 40 50 60 70 80 90 100 1k 100k 1m 10m LTC1409 ?f04 10k thd 3rd 2nd
10 LTC1409 applicatio n s i n for m atio n wu u u frequency (hz) 0 amplitude (db) 0 20 40 60 80 100 120 100k 200k 300k 400k LTC1409 ?f05 50k 150k 250k 350k fb ?fa 2fb ?fa 2fa ?fb 2fa 2fb 3fb fa + 2fb 3fa 2fa + fb fa + fb f sample = 800khz f in1 = 88.19580078khz f in2 = 111.9995117khz figure 5. intermodulation distortion plot value is expressed in decibels relative to the rms value of a full-scale input signal. full power and full linear bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. the full linear bandwidth is the input frequency at which the s/(n + d) has dropped to 68db (11 effective bits). the LTC1409 has been designed to optimize input bandwidth, allowing the adc to undersample input signals with fre- quencies above the converters nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) becomes dominated by distortion at frequencies far beyond nyquist. driving the analog input the differential analog inputs of the LTC1409 are easy to drive. the inputs may be driven differentially or as a single-ended input (i.e., the Ca in input is grounded). the +a in and Ca in inputs are sampled at the same instant. any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. during conversion the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low then the LTC1409 inputs can be driven directly. as source imped- ance increases so will acquisition time (see figure 6). for minimum acquisition time, with high source impedance, a buffer amplifier should be used. the only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conver- sion starts (settling time must be 150ns for full through- put rate). choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100 w ) at the closed-loop band- width frequency. for example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz should be less than 100 w . the second requirement is that the closed-loop source resistance (k w ) 0.01 acquisition time ( m s) 1 LTC1409 ?f06 0.1 0.01 0.1 110 100 10 figure 6. acquisition time vs source resistance
11 LTC1409 u s a o pp l ic at i wu u i for atio bandwidth must be greater than 20mhz to ensure adequate small-signal settling for full throughput rate. if slower op amps are used, more settling time can be provided by increasing the time between conversions. the best choice for an op amp to drive the LTC1409 will depend on the application. generally applications fall into two categories: ac applications where dynamic specifi- cations are most critical, and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the LTC1409, more detailed informa- tion is available in the linear technology databooks and the linearview tm cd-rom. lt ? 1220: 30mhz unity-gain bandwidth voltage feed- back amplifier. 5v to 15v supplies. excellent dc specifications, 90ns settling to 0.5lsb. lt1223: 100mhz video current feedback amplifier. 6ma supply current. 5v to 15v supplies. low distortion up to and above 400khz. low noise. good for ac applications. lt1227: 140mhz video current feedback amplifier. 10ma supply current 5v to 15v supplies. lowest distortion at frequencies above 400khz. low noise. best for ac applications. lt1229/lt1230: dual and quad 100mhz current feed- back amplifiers. 2v to 15v supplies. low noise. good ac specs. 6ma supply current for each amplifier. lt1360: 37mhz voltage feedback amplifier. 3.8ma sup- ply current. good ac/dc specs. 5v to 15v supplies. 70ns settling to 0.5lsb. lt1363: 50mhz, 450v/ m s op amps. 6.3ma supply cur- rent. good ac/dc specs. 60ns settling to 0.5lsb. lt1364/lt1365: dual and quad 50mhz, 450v/ m s op amps. 6.3ma supply current per amplifier. 60ns settling to 0.5lsb. input filtering the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1409 noise and distortion. the small-signal band- width of the sample-and-hold circuit is 20mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for example, figure 7 shows a 1000pf capacitor from + a in to ground and a 100 w source resistor to limit the input bandwidth to 1.6mhz. the 1000pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sam- pling glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. when high amplitude unwanted signals are close in fre- quency to the desired signal frequency, a multiple pole filter LTC1409 +a in ? in v ref refcomp agnd LTC1409 ?f07 1 2 3 4 5 ltc1560-1 1 2 3 4 8 7 6 5 10 m f 0.1 m f 5v 0.1 m f ?v v in figure 7b. 500khz 5th order elliptic lowpass filter linearview is a trademark of linear technology corporation. LTC1409 +a in ? in v ref refcomp agnd LTC1409 ?f07b 1 2 3 4 5 10 m f 1000pf 50 analog input figure 7a. rc input filter
12 LTC1409 u s a o pp l ic at i wu u i for atio is required. figure 7b shows a simple implementation using a ltc1560 5th order elliptic continuous time filter. input range the 2.5v input range of the LTC1409 is optimized for low noise and low distortion. most op amps also perform best over this same range, allowing direct coupling to the analog inputs and eliminating the need for special transla- tion circuitry. some applications may require other input ranges. the LTC1409 differential inputs and reference circuitry can ac- commodate other input ranges often with little or no addi- tional circuitry. the following sections describe the reference and input circuitry and how they affect the input range. internal reference the LTC1409 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500v. it is connected internally to a reference amplifier and is available at v ref (pin 3) see figure 8a. a 4k resistor is in series with the output so that it can be easily overdriven by an external reference or other cir- cuitry. the reference amplifier gains the voltage at the v ref pin by 1.625 to create the required internal reference voltage. this provides buffering between the v ref pin and the high speed capacitive dac. the reference amplifier compensation pin, refcomp (pin 4), must be bypassed with a capacitor to ground. the reference amplifier is stable with capacitors of 1 m f or greater. for the best noise performance, a 10 m f ceramic or 10 m f tantalum in parallel with 0.1 m f ceramic is recommended (see figure 8b). LTC1409 +a in analog input 5v ? in v ref refcomp agnd LTC1409 ?f08b 1 2 3 4 5 10 m f v in v out lt1019a-2.5 figure 8b. using the lt1019-2.5 as an external reference the v ref pin can be driven with a dac or other means shown in figure 9. this is useful in applications where the peak input signal amplitude may vary. the input span of the adc can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. the filtering of the internal LTC1409 reference amplifier will limit the bandwidth and settling time of this circuit. a settling time of 5ms should be allowed for, after a reference adjust- ment. r2 40k r3 64k reference amp 10 f refcomp agnd v ref r1 4k bangap reference 3 4 5 2.5v 4.0625v LTC1409 LTC1409 ?f08a figure 8a. LTC1409 reference circuit LTC1409 +a in analog input ? in v ref refcomp agnd LTC1409 ?f09 1 2 3 4 5 10 m f ltc1450 12-bit rail-to-rail dac 1.25v to 3v figure 9.driving v ref with a dac differential inputs the LTC1409 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. the adc will always convert the difference of +a in C (Ca in ) independent of the common mode voltage. the common mode rejection holds up to extremely high frequencies, see figure 10a. the only requirement is that both inputs can not exceed the av dd or av ss power supply voltages. integral nonlinearity errors (inl) and differential nonlinearity er- rors (dnl) are independent of the common mode voltage,
13 LTC1409 u s a o pp l ic at i wu u i for atio input frequency (hz) 1 common mode rejection (db) 80 70 60 50 40 30 20 10 0 10 100 LTC1409 ?tpc09 1000 10000 figure 10a. cmrr vs input frequency the output is twos complement binary with 1lsb = fs C (C fs)/4096 = 5v/4096 = 1.22mv. figure 10b. selectable 0v to 5v or 2.5v input range however, the bipolar zero error (bze) will vary. the change in bze is typically less than 0.1% of the common mode voltage. dynamic performance is also affected by the common mode voltage. thd will degrade as the inputs approach either power supply rail, from 86db with a common mode of 0v to 75db with a common mode of 2.5v or C 2.5v. differential inputs allow greater flexibility for accepting different input ranges. figure 10b shows a circuit that converts a 0v to 5v analog input signal with no additional translation circuitry. full-scale and offset adjustment figure 11a shows the ideal input/output characteristics for the LTC1409. the code transitions occur midway between successive integer lsb values (i.e., Cfs + 0.5lsb, Cfs + 1.5lsb, Cfs + 2.5lsb,. fs C 1.5lsb, fs C 0.5lsb). input range output code LTC1409 ?f11a 111...111 111...110 111...101 000...000 000...001 000...010 fs ?1lsb ?fs ?1lsb) figure 11a. LTC1409 transfer characteristics in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figure 11b shows the extra components required for full-scale error adjustment. zero offset is achieved by adjusting the offset applied to the C a in input. for zero offset error apply C 0.61mv (i.e., C 0.5lsb) at +a in and adjust the offset at the Ca in input until the output code flickers between 0000 0000 0000 and 1111 1111 1111. for full-scale adjust- ment, an input voltage of 2.49817v (fs/2 C 1.5lsbs) is applied to a in and r2 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. LTC1409 +a in analog input ? in v ref refcomp agnd LTC1409 ?f11b 1 2 3 r4 100 w r2 50k r3 24k ?v r6 24k r1 50k r5 47k 4 5 10 m f figure 11b. offset and full-scale adjust circuit LTC1409 +a in analog input ? in v ref refcomp agnd LTC1409 ?f10b 1 2 3 4 5 10 m f 2.5v 0v to 5v range 1 m f 2.5v range
14 LTC1409 u s a o pp l ic at i wu u i for atio board layout and bypassing wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the LTC1409, a printed circuit board with ground plane is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track. an analog ground plane separate from the logic system ground should be established under and around the adc. pin 5 (agnd), pin 14 and pin 19 (adcs dgnd) and all other analog grounds should be connected to this single analog ground point. the refcomp bypass capacitor and the ov dd bypass capacitor should also be connected to this analog ground plane. no other digital grounds should be connected to this analog ground plane. low impedance analog and digital power supply common returns are essential to low noise operation of the adc and the foil width for these tracks should be as wide as possible. in applications where the adc data outputs and control signals are connected to a continuously active micropro- cessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation com- parator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the LTC1409 has differential inputs to minimize noise coupling. common mode noise on the +a in and Ca in leads will be rejected by the input cmrr. the Ca in input can be used as a ground sense for the +a in input; the LTC1409 will hold and convert the difference voltage between +a in and Ca in . the leads to +a in (pin 1) and Ca in (pin 2) should be kept as short as possible. in applications where this is not possible, the +a in and Ca in traces should be run side- by-side to equalize coupling. supply bypassing high quality, low series resistance ceramic, 10 m f bypass capacitors should be used at the v dd and refcomp pins as shown in the typical application on the first page of this data sheet. surface mount ceramic capacitors such as murata grm235y5v106z016 provide excellent bypass- ing in a small board space. alternatively 10 m f tantalum capacitors in parallel with 0.1 m f ceramic capacitors can be used. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. example layout figure 13a, 13b, 13c and 13d show the schematic and layout of a suggested evaluation board. the layout demon- strates the proper use of decoupling capacitors and ground plane with a two layer printed circuit board. LTC1409 ?f12 +a in agnd refcomp av dd ov dd ognd LTC1409 digital system 0.1 m f + analog input circuitry 5 4 2 28 27 19 dgnd 14 1 0.1 m f 10 m f 10 m f ? in + v ss 26 0.1 m f 10 m f + + analog ground plane figure 12. power supply grounding practice
15 LTC1409 u s a o pp l ic at i wu u i for atio figure 13a. suggested evaluation circuit schematic + +a in ? in v ref refcomp agnd dgnd shdn rd convst cs busy v ss dv dd av dd 6 7 8 9 10 11 12 13 15 16 17 18 19 20 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 14 21 22 23 24 25 26 27 28 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ognd nap/slp u4 ltc1410 v cc j7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 gnd rdy gnd /d11 d1 d0 d3 d2 d5 d4 d7 d6 d9 d8 d11 d10 v kk d(0?1) data rdy v cc 20 u1 74hc374 d0 d1 d2 d3 d4 d5 d6 d7 3 4 7 8 13 14 17 18 1 11 d10 d9 d6 d0 d5 d7 d8 d11 2 5 6 9 12 15 16 19 d10 d9 d6 d0 d5 d7 d8 d11 d3 d4 d2 d1 0c q0 q1 q2 q3 q4 q5 q6 q7 clk v kk v cc 20 u2 74hc374 d0 d1 d2 d3 d4 d5 d6 d7 3 4 7 8 13 14 17 18 1 11 d3 d4 d2 d1 2 5 6 9 12 15 16 19 0c q0 q1 q2 q3 q4 q5 q6 q7 clk c3 0.1 m f c2 0.1 m f v ss + c9 10 m f 10v c11 10 m f 10v + 78 56 34 12 jp4 jp6 98 u3d 74hc14 r16 to r19 620 w d8 d9 d10 d11 jp3 r8 to r15 620 w d0 d1 d2 d3 d4 d5 d6 d7 c17 15pf r6 1k 13 12 u3f 74hc14 u3e 74hc14 11 10 1 1 2 u3a 74hc14 u3b 74hc14 34 56 u3c 74hc14 v cc v kk r7 20 w c4 0.1 m f c10 10 m f 10v c5 0.1 m f c6 0.1 m f c16 0.1 m f op-amp decoupling digital i.c. bypassing c15 0.1 m f v kk c9 0.001 m f npo 10% v ss v cc + c14 10 m f 10v notes: unless otherwise specified. 1. all resistor value ohms, 1/8w, 5%, smt. 2. all capacitor values m f, 50v, 20%, smt. 3. c14 may be replaced with a 10 m f, 25v, z5u, ceramic c7 0.1 m f c1 0.1 m f + c12 22 m f 10v + v cc v cc v cc 7 5 6 4 3 2 1 8 v ss u5 lt1360 r6 1k r4 51 w 12 jp1 1 1 2 jp2 j4 j6 j3 gnd j5 e1 v ref j1 7v to 15v v ref see note 3 r2 10k r2 10k r5 51 w tab u7 lt1121 1 1 2 4 3 v in out gnd d13 ss12 c13 22 m f 10v + v ss j2 ?v to ?5v u6 79l05 2 1 5 1 in out gnd d14 ss12
16 LTC1409 u s a o pp l ic at i wu u i for atio figure 13b. suggested evaluation circuit board component side silkscreen figure 13c. suggested evaluation circuit board component side layout
17 LTC1409 u s a o pp l ic at i wu u i for atio figure 13d. suggested evaluation circuit board solder side layout digital interface the a/d converter is designed to interface with micropro- cessors as a memory mapped device. the cs and rd control inputs are common to all peripheral memory interfacing. a separate convst is used to initiate a con- version. internal clock the a/d converter has an internal clock that eliminates the need of synchronization between the external clock and the cs and rd signals found in other adcs. the internal clock is factory trimmed to achieve a typical conversion time of 0.9 m s, and a maximum conversion time over the full operating temperature range of 1.15 m s. no external adjustments are required. the guaranteed maximum ac- quisition time is 150ns. in addition, a throughput time of 1250ns and a minimum sample rate of 800ksps is guaran- teed. power shutdown the LTC1409 provides two power shutdown modes, nap and sleep, to save power during inactive periods. the nap mode reduces the power by 95% and leaves only the digital logic and reference powered up. the wake-up time from nap to active is 200ns. in sleep mode all bias currents are shut down and only leakage current re- mains, about 1 m a. wake-up time from sleep mode is much slower since the reference circuit must power up and settle to 0.01% for full 12-bit accuracy. sleep mode wake-up time is dependent on the value of the capacitor connected to the refcomp (pin 4). the wake-up time is 10ms with the recommended 10 m f capacitor. shutdown is controlled by pin 21 (shdn). the adc is in shutdown when it is low. the shutdown mode is selected with pin 20 (nap/slp); high selects nap. timing and control conversion start and data read operations are controlled by three digital inputs: convst, cs and rd. a logic 0 applied to the convst pin will start a conversion after the adc has been selected (i.e., cs is low). once initiated, it cannot be restarted until the conversion is complete. converter status is indicated by the busy output. busy is low during a conversion. figures 16 through 20 show several different modes of operation. in modes 1a and 1b (figures 16 and 17) cs and rd are both tied low. the falling edge of convst starts the conversion. the data outputs are always enabled and data
18 LTC1409 u s a o pp l ic at i wu u i for atio t 3 nap/slp shdn LTC1409 ?f14a figure 14a. nap/slp to shdn timing t 2 t 1 cs convst rd LTC1409 ?f15 figure 15. cs to convst setup timing t 4 shdn convst LTC1409 ?f14b figure 14b. shdn to convst wake-up timing data (n ?1) db11 to db0 convst busy LTC1409 ?f16 t 5 t conv t 6 t 8 t 7 data n db11 to db0 data (n + 1) db11 to db0 data figure 16. mode 1a. convst starts a conversion. data outputs always enabled (convst = ) can be latched with the busy rising edge. mode 1a shows operation with a narrow logic low convst pulse. mode 1b shows a narrow logic high convst pulse. in mode 2 (figure 18) cs is tied low. the falling edge of convst signal again starts the conversion. data outputs are in three-state until read by the mpu with the rd signal. mode 2 can be used for operation with a shared mpu databus. in slow memory and rom modes (figures 19 and 20) cs is tied low and convst and rd are tied together. the mpu starts the conversion and reads the output with the rd signal. conversions are started by the mpu or dsp (no external sample clock). in slow memory mode the processor applies a logic low to rd (= convst) starting the conversion. busy goes low forcing the processor into a wait state. the previous conversion result appears on the data outputs. when the conversion is complete, the new conversion results ap- pear on the data outputs; busy goes high releasing the processor, and the processor takes rd (= convst) back high and reads the new conversion data. in rom mode, the processor takes rd (= convst) low, starting a conversion and reading the previous conversion result. after the conversion is complete, the processor can read the new result and initiate another conversion.
19 LTC1409 u s a o pp l ic at i wu u i for atio data (n ?1) db11 to db0 convst busy LTC1409 ?f17 t conv t 6 t 13 t 7 cs = rd = 0 data n db11 to db0 data (n + 1) db11 to db0 data t 6 t 5 t 8 figure 17. mode 1b. convst starts a conversion. data outputs always enabled convst busy LTC1409 ?f18 t 5 t conv t 8 t 13 t 6 t 9 t 12 data n db11 to db0 t 11 t 10 rd data figure 18. mode 2. convst starts a conversion. data is read by rd figure 20. rom mode timing rd = convst busy LTC1409 ?f20 t conv t 6 data (n ?1) db11 to db0 data data n db11 to db0 t 10 t 11 t 8 rd = convst busy LTC1409 ?f19 t conv t 6 data (n ?1) db11 to db0 data data n db11 to db0 data (n + 1) db11 to db0 data n db11 to db0 t 11 t 8 t 10 t 7 figure 19. slow memory mode timing
20 LTC1409 ? linear technology corporation 1995 1409f lt/tp 0397 7k ? printed in usa u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 l (408) 432-1900 fax: (408) 434-0507 l telex: 499-3977 l www.linear-tech.com g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) g28 ssop 0694 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 14 13 0.397 ?0.407* (10.07 ?10.33) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** sw package 28-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620) s28 (wide) 0996 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ note 1 0.697 ?0.712* (17.70 ?18.08) 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 25 26 11 12 22 21 20 19 18 17 16 15 23 24 14 13 27 28 note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** related products part number description comments ltc1273/75/76 complete 5v sampling 12-bit adcs with 70db sinad at nyquist 300ksps, single or dual supplies ltc1274/77 low power 12-bit adcs with nap and sleep mode shutdown 100ksps, 8-bit or 12-bit digital i/o ltc1278/79 high speed sampling 12-bit adcs with shutdown 500ksps/600ksps, single or dual supplies ltc1282 complete 3v 12-bit adc with 12mw power dissipation fully specified for 3v/ 3v supply ltc1410 high speed sampling 12-bit adc 1.25msps, 71db sinad at nyquist, low power ltc1415 high speed sampling 12-bit adc 1.25msps, single 5v supply, lowest power ltc1419 14-bit, 800ksps sampling adc 81.5db sinad, 150mw from 5v supplies ltc1605 16-bit, 100ksps sampling adc single supply, 10v input range, low power

▲Up To Search▲

Price & Availability of LTC1409

	To Download LTC1409 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .